View MT9V111D00STCK82AC1K-305_8253215.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

mt9v111 - 1/4-inch soc vga digital image sensor features mt9v111_ds rev. n 5/15 en 1 ?semiconductor components industries, llc 2015, 1/4-inch soc vga cmos active-pixel digital image sensor mt9v111 datasheet, rev. n for the latest data sheet revision, please visit www.onsemi.com features ? system-on-a-chip (soc)?completely integrated camera system ? ultra low-power, low cost cmos image sensor ? superior low-light performance ? up to 30 fps progressive scan at 27 mhz for high- quality video at vga resolution ? on-chip image flow pr ocessor (ifp) performs sophisticated processing: color recovery and correction, sharpening, gamma, lens shading correction, on-the-fly defect correction, 2x fixed zoom ? image decimation to arbi trary size with smooth, continuous zoom and pan ? automatic exposure, white balance and black compensation, flicker avoidance, color saturation, and defect identification and correction, auto frame rate, back light compensation ? xenon and led-type flash support ? two-wire serial programming interface ? itu_r bt.656 (ycbcr), yuv, 565rgb, 555rgb, and 444rgb output data formats applications ? cellular phones ?pdas ?pc camera ? toys and other battery-powered products general description the on semiconductormt9v111 is a 1/4-inch vga-for- mat cmos active-pixel digital image sensor, the result of combining the mt9v011 image sensor core with on semiconductor's third-generation digital image flow processor technology. the mt9v111 has an active imag- ing pixel array of 649 x 489, capturing high-quality color images at vga resolution. the sensor is a complete camera-on-a-chip solution and is designed specifically to meet the demands of battery-powered products such as cellular phones, pdas, and toys. it incorporates sophisticated camera functions on-chip and is pro- grammable through a simple two-wire serial interface. table 1: key performance parameters parameter value optical format 1/4-inch (4:3) active imager size 3.58mm(h) x 2.69mm(v) 4.48mm (diagonal) active pixels 640h x 480v (vga) pixel size 5.6 um x 5.6 um color filter array rgb bayer pattern shutter type electronic rolling shutter (ers) maximum data rate/ master clock 12 ? 13.5 mps/24 ? 27 mhz frame rate vga (640 x 480) 15 fps at 12 mhz (default), programmable up to 30 fps at 27 mhz cif (352 x 288) programmable up to 60 fps qvga (320 x 240) programmable up to 90 fps adc resolution 10-bit, on-chip responsivity 1.9 v/lux-sec (550nm) dynamic range 60 db snr max 45 db supply voltage 2.8v + 0.25v power consumption <80 mw at 2.8 v, 15 fps at 12 mhz operating temperature -20c to +60c packaging 44-ball icsp, wafer or die
mt9v111_ds rev. n 5/15 en 2 ?semiconductor components industries, llc,2015. mt9v111 - 1/4-inch soc vga digital image sensor ordering information ordering information table 2: available part numbers part number product description orderable product attribute description mt9v111d00atck82ac1-305 vga 1/4" soc die sales, 305 ? m thickness MT9V111D00STCK82AC1K-305 vga 1/11" soc die sales, 305 ? m thickness mt9v111ia7atc-dp vga 1/13" soc dry pack with protective film mt9v111ia7atc-dr vga 1/4" soc dry pack without protective film mt9v111ia7atc-tp vga 1/4" cis soc tape & reel with protective film mt9v111ia7atc-tr vga 1/4" soc tape & reel without protective film
mt9v111_ds rev. n 5/15 en 3 ?semiconductor components industries, llc,2015. mt9v111 - 1/4-inch soc vga digital image sensor table of contents table of contents applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 ordering information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 ball assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 image flow processor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 output data ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 sensor core overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 electrical specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 propagation delays. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 appendix a ? sensor timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 serial bus description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 two-wire serial interface sam ple write and read sequences (with saddr = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 appendix b ? overview of programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
mt9v111_ds rev. n 5/15 en 4 ?semiconductor components industries, llc,2015. mt9v111 - 1/4-inch soc vga digital image sensor list of figures list of figures figure 1: chip block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 figure 2: internal register grouping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 figure 3: typical configuration (connection) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 figure 4: 44-ball icsp package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 figure 5: image flow processor bl ock diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 figure 6: sensor core block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 figure 7: pixel array description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 figure 8: pixel color pattern detail (top right corner) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 figure 9: spatial illustration of image re adout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 figure 10: propagation delays for pixclk and data out signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 figure 11: propagation delays for frame_vali d and line_valid signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 7 figure 12: data output timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 figure 13: spectral response. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 figure 14: die center - image centeroffset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 figure 15: row timing and frame_valid/line_valid signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 figure 16: timing diagram showing a write to reg0x09 with value 0x0284 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 figure 17: timing diagram showing a read from reg0x09; return ed value 0x0284 . . . . . . . . . . . . . . . . . . . . . . .23 figure 18: timing diagram showing a bytewise write to reg0x09 with value 0x0284. . . . . . . . . . . . . . . . . . . . . .24 figure 19: timing diagram showing a byte wise read from reg0x09; returned value 0x0284 . . . . . . . . . . . . . .24 figure 20: serial host interface start condition timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 figure 21: serial host interface stop condition timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 figure 22: serial host interface data timing for write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 figure 23: serial host interface data timing for read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 figure 24: acknowledge signal timing after an 8-bit write to th e sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 figure 25: acknowledge signal timing after an 8-bit read from th e sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 figure 26: 44-ball icsp package outline drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
mt9v111_ds rev. n 5/15 en 5 ?semiconductor components industries, llc,2015. mt9v111 - 1/4-inch soc vga digital image sensor list of tables list of tables table 1: key performance parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 table 2: available part numbers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 table 2: ball description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 table 3: yuv/ycbcr output data ordering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 table 4: rgb output data ordering in default mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 table 5: byte ordering in 8 + 2 bypass mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 table 6: dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 table 7: ac electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 table 8: frame time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 table 9: frame time?larger than one frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 table 10: non-default register settings optimizing 15 fps at 12 mhz operation . . . . . . . . . . . . . . . . . . . . . . . .27 table 11: non-default register settings optimizing 30 fps at 27 mhz operation . . . . . . . . . . . . . . . . . . . . . . . .27 table 12: relation between ifp r55[9:5] setting and frame rate ra nge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 table 13: decimation, zoom, and pan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 table 14: ycbcr settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 table 15: yuv settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
mt9v111_ds rev. n 5/15 en 6 ?semiconductor components industries, llc,2015. mt9v111 - 1/4-inch soc vga digital image sensor general description general description this soc vga cmos image sensor features on semiconductor?s breakthrough, low- noise cmos imaging technology that achiev es ccd image quality (based on signal-to- noise ratio and low-light sensitivity) while maintaining the inherent size, cost and inte- gration advantages of cmos. the mt9v111 is a fully-automatic, single-chip camera, requiring only a power supply, lens and clock source for basic operation. ou tput video is streamed via a parallel eight- bit d out port as shown in figure 1. output pixel clock is used to latch the data, while frame_valid and line_valid signals indicate the active video. the sensor can be put in an ultra-low power sleep mode by assert ing the standby pin. output pads can also be tri-stated by de-asserting the oe# pin. the mt9v111 internal registers can be config- ured using a two-wire serial interface. the mt9v111 can be programmed to output progressive scan images up to 30 fps in an 8-bit itu_r bt.656 (ycbcr) formerly ccir656, yuv, 565rgb, 555rgb, or 444rgb formats. the frame_valid and line_valid signals are output on dedicated pins, along with a pixel clock that is synchronous with valid data. figure 1: chip block diagram the mt9v111 can accept the input clock of up to 27 mhz, delivering 30 fps. with power- on defaults (see appendix b for recommende d defaults), the camera is configured to deliver 15 fps at 12 mhz and automatically slows down the frame rate in low-light condi- tions to achieve longer exposures and better image quality. internally, the mt9v111 consists of a sensor core and an image flow processor. the sensor core functions to capture raw bayer-encoded images that are input into the ifp as shown in figure 1. the ifp processes the incoming stream to create interpolated, color-corrected output and controls the sensor core to maintain the desirable exposure and color balance. sensor core and ifp registers are grouped into two separate address spaces, as shown in figure 2. the internal registers can be accessed via the two-wire serial interface. selecting the desired address space can be accomplished by programming register r1 which remains present in both register sets. d out (7:0) pixclk frame_valid line_valid flash communication bus sensor core . based on mt9v011 . 668h x 496v (vga+ reference) . 1/4-inch optical format . auto black compensation . programmable analog gain . programmable exposure . low power, 10-bit adcs sram line buffers image flow processor . color correction, gamma, lens shading correction . auto exposure, white balance . interpolation and defect correction . flicker avoidance sclk s data s addr clk standby oe# v dd /d gnd v aa /a gnd vaapix
mt9v111_ds rev. n 5/15 en 7 ?semiconductor components industries, llc,2015. mt9v111 - 1/4-inch soc vga digital image sensor general description figure 2: internal register grouping note: program r1 to select the desired space (4 = sensor core registes, 1 = ifp/soc registers). figure 3 shows mt9v111 typical connections. for low-noise operation, the mt9v111 requires separate supplies for analog and di gital power. incoming digital and analog ground conductors can be tied together righ t next to the die. both power supply rails should be decoupled to ground using capaci tors. the use of inductance filters is not recommended. figure 3: typical configuration (connection) note: 1.5k ? resistor value is recommended, but may be greater for slower two-wire speed. r0 r1 sensor core registers (r2..r255 ) r1=4 r0 r1 ifp registers (r2..r255 ) r1=1 d out (7:0) frame_valid line_valid pixclk flash to cmos camera port d gnd a gnd to xenon flash trigger or led enable v dd v aa 10f master clock two-wire serial bus { { a gnd d gnd s addr reset# s data sclk clkin scan_en oe# standby v dd v aa vaapix adc_test 1k 1.5k 1.5k
mt9v111_ds rev. n 5/15 en 8 ?semiconductor components industries, llc,2015. mt9v111 - 1/4-inch soc vga digital image sensor ball assignment ball assignment figure 4: 44-ball icsp package table 2: ball description ball numbers name type description g2 clkin input master clock into sensor. default is 12 mhz (27 mhz maximum). f3 sclk input serial clock. f4 s addr input serial interface address select: reg0xb8 when high (default). reg0x90 when low. f6 adc_test input tie to vaapix (factory use only). e6 reset# input asynchronous reset of sensor when low. all registers assume factory defaults. e7 standby input when high puts the imag er in ultra-low power standby mode. d6 oe# input output_enable_bar pin. when high tri-state all outputs except s data (tie low for normal operation). c6 scan_en input tie to digital ground. g3 s data i/o serial data i/o. e2 flash output flash strobe. e1 pixclk output pixel clock out. pixel data output are valid during rising edge of this clock. ifp reg0x08 [9] inverts polarity. frequency = master clock. e3 line_valid output active high during line of selectable valid pixel data. f1 frame_valid output active high during frame of valid pixel data. b5 d out 7 output itu_r bt.656/rgb data bit 7 (msb). a b c d e f g 2 d out 2 v dd d out 0 nc flash v dd clkin 3 d out 4 d out 3 d out 5 line_ sclk s data 1 d gnd d out 1 nc d gnd pixclk frame_ valid d gnd 4 d gnd v dd s addr d gnd 6 v dd v dd scan oe# reset# adc_ v aa 7 d gnd v dd d gnd d gnd stand vaapix a gnd 5 d out 6 d out 7 v dd v dd a gnd v aa top view (ball down) by valid _en test
mt9v111_ds rev. n 5/15 en 9 ?semiconductor components industries, llc,2015. mt9v111 - 1/4-inch soc vga digital image sensor ball assignment a5 d out 6 output itu_r bt.656/rgb data bit 6. c3 d out 5 output itu_r bt.656/rgb data bit 5. a3 d out 4 output itu_r bt.656/rgb data bit 4. b3 d out 3 output itu_r bt.656/rgb data bit 3. a2 d out 2 output itu_r bt.656/rgb data bit 2. b1 d out 1 output itu_r bt.656/rgb data bit 1. c2 d out 0 output itu_r bt.656/rgb data bit 0 (lsb). a6,b2,b4,b6 , b7,c5,e5,f2 v dd supply digital power (2.8v). g5,g6 v aa supply analog power (2.8v). f7 vaapix supply pixel array power (2.8v). f5,g7 a gnd supply analog ground. a1,d1,a4,a 7,c7,d7,g1, g4 d gnd supply digital ground. c1,d2 nc ? no connect. table 2: ball description (continued) ball numbers name type description
mt9v111_ds rev. n 5/15 en 10 ?semiconductor components industries, llc,2015. mt9v111 - 1/4-inch soc vga digital image sensor image flow processor image flow processor overview of architecture the image flow processor consists of a color processing pipeline and a measurement and control logic block as shown in figure 5. the stream of raw data from the sensor enters the pipeline and undergoes a numb er of transformations. image stream processing starts from conditioning the black level and applying a digital gain. the lens shading block compensates for signal loss caused by the lens. next, the data is interpo- lated to recover missing color components for each pixel and defective pixels are corrected. the resulting interpolated rgb da ta passes through the current color correc- tion matrix (ccm), gamma, and saturation corrections and is formatted for final output. the measurement and control logic continuo usly accumulates statistics about image brightness and color. indoor 50/60 hz flic ker is detected and automatically updated when possible. based on these measurements the ifp calculates updated values for exposure time and sensor analog gains, wh ich are sent to the sensor core via the communication bus. color correction is achieved through linear transformation of the image with a 3 x 3 color correction matrix. color saturation can be adjusted in the range from zero (black and white) to 1.25 (125% of full color saturation). gamma correction compensates for non-linear dependence of the display device output vs. driving signal (e.g. monitor brightness vs. crt voltage). output and formatting processed video can be output in the form of a standard itu_r bt.656 or rgb stream. itu_r bt.656 (default) stream contains 4:2:2 data with optional embedded synchroniza- tion codes. this kind of output is typically suitable for subsequent display by standard video equipment. for jpeg/mpeg compression, yuv/ encoding is suitable. rgb func- tionality is provided to support lcd device s. the mt9v111 can be configured to output 16-bit rgb (rgb565), 15-bit rgb (rgb555) as well as two types of 12-bit rgb (rgb444). the user can configure internal registers to swap odd and even bytes, chrominance channels and luminance and chrominance components to facilitate interface to appli- cation processors.
mt9v111_ds rev. n 5/15 en 11 ?semiconductor components industries, llc,2015. mt9v111 - 1/4-inch soc vga digital image sensor image flow processor figure 5: image flow processor block diagram the mt9v111 features smooth, continuous zo om and pan. this functionality is avail- able when the ifp output is downsized in the decimation block. the decimation block can downsize the original vga image to any integer size, including qvga, qqvga, cif and qcif with no loss to the field of view. the user can program the desired size of the output image in terms of horizontal and vertical pixel count. in addition the user can program the size of a region for downsizing. continuous zoom is achieved every time the region of interest is less than the entire vga image. the maximum zoom factor is equal to the ratio of vga to the size of the region of interest. for example, an image rendered on a 160x120 display can be zoomed by 640/160=480/120=4 times. continuous pan is achieved by adjusting the starting coordinates of the region of interest. also a fixed 2x up-zoom is implemented by means of windowing down the sensor core. in this mode the ifp receives a qvga-sized input data and outputs a vga-size image. the sub-window can be panned both vertically and horizontally by programming sensor core registers. the mt9v111 supports both led and xenon-ty pe flash light sources using a dedicated output pad. for xenon devices the pad generates a strobe to fire when the imager's shutter is fully open. for led the pad can be asserted or de-asserted asynchronously. flash modes are configured and engaged over the two-wire serial interface using ifp reg0x98. ima g e s en s or g amma c orre c tion c olor c orre c tion demo s ai c in g output formattin g fla s h c ontrol ae, awb, fli c ker avoidan c e len s c orre c tion
mt9v111_ds rev. n 5/15 en 12 ?semiconductor components industries, llc,2015. mt9v111 - 1/4-inch soc vga digital image sensor output data ordering output data ordering in ycbcr the first and second bytes can be swapped. luma/chroma bytes can be swapped as well. r and b channe ls are bit-wise swapped when chroma swap is enabled. see ifp reg0x3a for channel swapping configuration. table 4: rgb output data ordering in default mode a bypass mode is available whereby raw bayer 10-bits data is output as two bytes. see ifp reg8[7]. table 5: byte ordering in 8 + 2 bypass mode table 3: yuv/ycbcr output data ordering mode 1st byte 2nd byte 3rd byte 4th byte default (no swap) cb i y i cr i y i+1 swapped crcb cr i y i cb i y i+1 swapped yc y i cb i y i+1 cr i swapped crcb, yc y i cr i y i+1 cb i mode (swap disabled) byte d7 d6 d5 d4 d3 d2 d1 d0 rgb 565 first r7 r6 r5 r4 r3 g7 g6 g5 second g4 g3 g2 b7 b6 b5 b4 b3 rgb 555 first0 r7r6r5r4r3g7g6 second g4 g3 g2 b7 b6 b5 b4 b3 rgb 444x first r7 r6 r5 r4 g7 g6 g5 g4 secondb7b6b5b40000 rgb x444 first 0 0 0 0 r7 r6 r5 r4 second g7 g6 g5 g4 b7 b6 b5 b4 byte ordering 8+2 bypass firstd9d8d7d6d5d4d3d2 second000000d1d0
mt9v111_ds rev. n 5/15 en 13 ?semiconductor components industries, llc,2015. mt9v111 - 1/4-inch soc vga digital image sensor sensor core overview sensor core overview the sensor consists of a pixel array of 668 x 496 total, analog readout chain, 10-bit adc with programmable gain and black offset, and timing and control. note: see sensor core (mt9v011) data sheet for more details. figure 6: sensor core block diagram the sensor core?s pixel array is configured as 668 columns by 496 rows (shown in figure 7). the first 18 columns and the first 6 rows of pixels are optically black and can be used to monitor the black level. the last colu mn and the last row of pixels are also opti- cally black. the black row data is used internally for the automatic black level adjust- ment. there are 649 columns by 489 rows of optically active pixels, which provides a four-pixel boundary around the vga (640 x 480) image to avoid boundary affects during color interpolation and correcti on. the additional active column and additional active row are used to allow horizontally and vertically mirrored readout to also start on the same color pixel, as shown in figure 7. figure 7: pixel array description the sensor core uses the rgb bayer color pattern (shown in figure 8). even-numbered rows contain green and red color pixels, and odd-numbered rows contain blue and green color pixels. even-numbered columns contain green and blue color pixels; odd- numbered columns contain red and green color pixels. a c tive pixel s ensor array c ontrol re g ister analo g pro c essin g timin g an d c ontrol ad c c ommuni c ation bus to ifp 10- b it data to ifp c lo c k s yn c . s i g nals (667,495) 18 black columns 1 black row 6 black rows (0, 0) 1 black column vga (640 x 480) + 4 pixel boundary for color correction + additional active column + additional active row = 649 x 489 active pixels
mt9v111_ds rev. n 5/15 en 14 ?semiconductor components industries, llc,2015. mt9v111 - 1/4-inch soc vga digital image sensor sensor core overview figure 8: pixel color pattern detail (top right corner) the sensor core image data is read-out in a progressive scan. valid image data is surrounded by horizontal and vertical blan king, as shown in figure 9. the amount of horizontal and vertical blanking is progra mmable through the sensor core registers reg0x05 and reg0x06, respectively. line_valid is high during the shaded region of the figure. see ?appendix a ? sensor timing? on page 20 for the description of frame_valid timing. figure 9: spatial illustration of image readout notes: 1. do not change these registers. contact on semiconductor support for settings different from defaults. 2. ifp controls these registers when ae, awe, or flicker avoidance are enabled. pixel (18, 6 ) (first opti c al c lear pixel) b la c k pixels c olumn rea d out d ire c tion . . . . . . ... row rea d out d ire c tion g b g b g b r g r g r g g b g b g b r g r g r g g b g b g b r g r g r g g b g b g b p 0,0 p 0,1 p 0,2 .....................................p 0,n-1 p 0,n p 1,0 p 1,1 p 1,2 .....................................p 1,n-1 p 1,n 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 p m-1,0 p m-1,1 .....................................p m-1,n-1 p m-1,n p m,0 p m,1 .....................................p m,n-1 p m,n 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 00 00 00 ..................................... 00 00 00 00 00 00 ..................................... 00 00 00 00 00 00 ..................................... 00 00 00 00 00 00 ..................................... 00 00 00 valid image horizontal blanking vertical blanking vertical/horizontal blanking
mt9v111_ds rev. n 5/15 en 15 ?semiconductor components industries, llc,2015. mt9v111 - 1/4-inch soc vga digital image sensor electrical specifications electrical specifications the recommended die operating temperature ranges from -20 c to +40 c. the sensor image quality may degrade above +40c. notes: 1. to place the chip in standby mode, first raise standby to v dd , then wait two master clock cycles before turning off the master clock. two master clock cycles are required to place the analog cir- cuitry into standby, low-power mode. 2. when standby is de-asserted, standby mode is ex ited immediately (within several master clocks), but the current frame and the next two frames will be invalid. the fourth frame will contain a valid image. table 6: dc electrical characteristics v dd = v aa = 2.8 0.25v; t a = 25 c symbol definition condition min typ max unit v ih input high voltage v dd - 0.25 v dd + 0.25 v v il input low voltage -0.3 0.8 v i in input leakage current no pull-up resistor; v in = v dd or d gnd -5 5.0 ? a v oh output high voltage v dd - 0.2 v v ol output low voltage 0.2 v i oh output high current 15.0 ma i ol output low current 20.0 ma i oz tri-state output leakage current 5.0 ? a i aa analog operating supply current default settings, c load = 10pf clkin = 12 mhz clkin = 27 mhz 10.0 10.0 20.0 20.0 25.0 25.0 ma i dd digital operating supply current default settings, c load = 10pf clkin = 12 mhz clkin = 27 mhz 5.0 10.0 8.0 15.0 20.0 20.0 ma i aa standby analog standby supply current stdby = v dd 0.0 2.5 5.0 ? a i dd standby digital standby supply current stdby = v dd 0.0 2.5 5.0 ? a
mt9v111_ds rev. n 5/15 en 16 ?semiconductor components industries, llc,2015. mt9v111 - 1/4-inch soc vga digital image sensor electrical specifications notes: 1. for 30 fps operation with a 27 mhz clock, it is very important to have a precise duty cycle equal to 50%. with a slower frame rate and a slower clock the clock duty cycle can be relaxed. table 7: ac electrical characteristics v dd = v aa = 2.8 0.25v; t a = 25 c symbol definition condition min typ max unit f clkin input clock frequency 12 27 mhz clock duty cycle 45 50 55 % t r input clock rise time 2.0 ns t f input clock fall time 2.0 ns t plh p t phl p clkin to pixclk propagation delay: low-to-high high-to-low c load = 10pf 12 10 ns t dsetup t dhold pixclk to d out (7:0) at 27 mhz setup time hold time c load = 10pf 13.0 13.0 ns t dsetup t dhold pixclk to d out (7:0) at 12 mhz setup time hold time c load = 10pf 25.0 25.0 ns t oh data hold time from pixclk falling edge 9.0 ns t plh f , l t phl f , l clkin to frame_valid and line_valid propagation delay: low-to-high high-to-low c load = 10pf 9.0 7.5 ns t out routput rise time c load = 10pf 7.0 ns t out f output fall time c load = 10pf 9.0 ns
mt9v111_ds rev. n 5/15 en 17 ?semiconductor components industries, llc,2015. mt9v111 - 1/4-inch soc vga digital image sensor propagation delays propagation delays propagation delays for pixc lk and data out signals the typical output delay, relative to the mast er clock edge, is 7.5 ns. note that the data outputs change on the falling edge of the mast er clock, with the pixel clock rising on the subsequent rising edge of the master clock. propagation delays for frame_valid and line_valid signals the line_valid and frame_valid signals ch ange on the same falling master clock edge as the data output. the line_valid go es high on the same falling master clock edge as the output of the first valid pixel' s data and returns low on the same master clock falling edge as the end of the ou tput of the last valid pixel's data. as shown in figure 12, data output timing diagram, on page 18, frame_valid goes high 6 pixel clocks prior to the time that the first line_valid goes high. it returns low at a time corresponding to 6 pixel clocks after the last line_valid goes low. figure 10: propagation delays for pixclk and data out signals figure 11: propagation delays for frame_valid and line_valid signals d out (7:0) d out (7:0) d out (7:0) d out (7:0) d out (7:0) clkin pixclk t plh d , t phl d t plh p t r t f t phl p t oh clkin f rame_valid line_valid clkin frame_valid line_valid t plh f, l t phl f, l
mt9v111_ds rev. n 5/15 en 18 ?semiconductor components industries, llc,2015. mt9v111 - 1/4-inch soc vga digital image sensor propagation delays figure 12: data output timing diagram note: pixclk = max 27 mhz t fvsetup = / setup time for frame_valid before rising edge of pixclk / = 18ns t fvhold = / hold time for frame_valid after rising edge of pixclk / = 18ns t lvsetup = / setup time for line_valid before rising edge of pixclk / = 18ns t lvhold = / hold time for line_valid after rising edge of pixclk / = 18ns t dsetup = / setup time for d out before rising edge of pixclk / = 13ns t dhold = / hold time for d out after rising edge of pixclk / = 13ns frame start: ff00 00a0 line start: ff00 0080 line end: ff00 0090 frame end: ff00 00b0 pixclk frame_valid line_valid d out (7:0) t dsetup t dhold t fvhold t lvhold cb 0 y 1 cr 0 y last y last cb 0 cb 0 y 0 t fvsetup t lvsetup
mt9v111_ds rev. n 5/15 en 19 ?semiconductor components industries, llc,2015. mt9v111 - 1/4-inch soc vga digital image sensor propagation delays figure 13: spectral response figure 14: die center - image centeroffset note: not to scale. 0.0 0.2 0.4 0.6 0.8 1.0 1.2 350 450 550 650 750 850 950 1050 wavelength (nm) relative response blue green (b) green (r) red relative response array array array array pixel (0, 0) die center - direction + direction + direction - direction 11.0um -91.3um 0 0 pixel array center
mt9v111_ds rev. n 5/15 en 20 ?semiconductor components industries, llc,2015. mt9v111 - 1/4-inch soc vga digital image sensor appendix a C sensor timing appendix a C sensor timing figure 15: row timing and frame_valid/line_valid signals note: the signals in figure 15 are defined in table 8. note: in order to avoid flicker, frame time is 65.65ms. sensor timing is shown above in terms of ma ster clock cycle. the vertical blanking and total frame time equations assume that the number of integration rows (bits 11 through 0 of reg0x09) is less than the number of ac tive row plus blanking rows (reg0x03 + 1 + reg0x06 + 1). if this is not the case, the numb er of integration rows must be used instead to determine the frame time, as shown in table 9. table 8: frame time parameter name equation (master clocks) default timing at 12 mhz a active data time (reg0x04 - 7) x 2 = 1,280 pixel clocks = 1,280 master clocks = 106.7us p1 frame start blanking (reg0x05 + 112) x 2 = 300 pixel clocks = 300 master clocks = 25.0us p2 frame end blanking 14 clks = 14 pixel clocks = 14 master clocks = 1.17us q horizontal blanking (reg0x05 + 121) x 2 (min reg0x05 value = 9) = 318 pixel clocks = 318 master clocks = 26.5us a + q row time (reg0x04 + reg0x05 +114) x 2 = 1,598 pixel clocks = 1,598 master clocks = 133.2us v vertical blanking (reg0x06 + 9) x (a + q) + (q - p1 - p2) = 20, 778 pixel clocks = 20,778 master clocks = 1.73ms nrows x (a + q) frame valid time (reg0x03 - 7) x (a + q) - (q - p1 - p2) = 767,036 pixel clocks = 767,036 master clocks = 63.92ms f total frame time (reg0x03 + reg0x06 + 2) x (a + q) = 787,814 pixel clocks = 787,814 master clocks = 65.65ms table 9: frame time ? larger than one frame parameter name equation (master clocks) default timing v vertical blanking (long integration time) (reg0x09 - reg0x03) x (a + q) C f total frame time (long integration time) (reg0x09 + 1) x (a + q) C p1 a q a q ap2 number of master clocks frame_valid line_valid ... ... ...
mt9v111_ds rev. n 5/15 en 21 ?semiconductor components industries, llc,2015. mt9v111 - 1/4-inch soc vga digital image sensor serial bus description serial bus description registers are written to and read from the mt9v111 through the two-wire serial inter- face bus. the sensor is a serial interface slave and is controlled by the serial clock (sclk), which is driven by the serial interface master. data is transferred into and out of the mt9v111 through the serial data (s data ) line. the s data line is pulled up to 2.8v off- chip by a 1.5k ? resistor. either the slave or master device can pull the s data line down? the serial interface protocol determines which device is allowed to pull the s data line down at any given time. the registers are 16 bits wide and can be accessed through 16- bit or eight-bit two-wire serial bus sequences. protocol the two-wire serial interface defines several different transmission codes, as follows: ?a start bit ? the slave device eight-bit address. s addr is used to select between two different addresses in case of conflict with another device. if s addr is low, the slave address is 0x90; if s addr is high, the slave address is 0xb8. ? a(n) (no) acknowledge bit ? an eight-bit message ?a stop bit sequence a typical read or write sequence begins by th e master sending a start bit. after the start bit, the master sends the slave device's eigh t-bit address. the last bit of the address determines if the request will be a read or a write, where a "0" indicates a write and a "1" indicates a read. the slave device acknowledges its address by sending an acknowledge bit back to the master. if the request was a write, the master then transfers the 8-bit register address to which a write should take place. the sl ave sends an acknowledge bit to indicate that the register address has been received. the master then tr ansfers the data eight bits at a time, with the slave sending an acknowledge bit after each 8 bits. the mt9v111 uses 16-bit data for its internal registers, thus requiring two eight-bit transfers to write to one register. after 16 bits are transferred, the register address is automatically incremented, so that the next 16 bits are written to the next register addr ess. the master stops writing by sending a start or stop bit. a typical read sequence is executed as follows. first the master sends the write-mode slave address and eight-bit register address, just as in the write request. the master then sends a start bit and the read-mode slave address. the master then clocks out the register data eight bits at a time. the mast er sends an acknowledge bit after each eight- bit transfer. the register address is auto-inc remented after every 16 bits is transferred. the data transfer is stopped when th e master sends a no-acknowledge bit. the mt9v111 allows for eight-bit data transfer s through the two-wire serial interface by writing (or reading) the most significant eigh t bits to the register and then writing (or reading) the least significant eight bits to reg0x7f (127). bus idle state the bus is idle when both the data and cloc k lines are high. control of the bus is initi- ated with a start bit, and the bus is released with a stop bit. only the master can generate the start and stop bits.
mt9v111_ds rev. n 5/15 en 22 ?semiconductor components industries, llc,2015. mt9v111 - 1/4-inch soc vga digital image sensor serial bus description start bit the start bit is defined as a high-to-low transi tion of the data line while the clock line is high. stop bit the stop bit is defined as a low-to-high transi tion of the data line while the clock line is high. slave address the 8-bit address of a two-wire serial interfac e device consists of seven bits of address and 1 bit of direction. a ?0? in the least sign ificant bit (lsb) of the address indicates write mode, and a ?1? indicates read mode. the write address of the sensor is 0xb8, while the read address is 0xb9; this only applies when s addr is set high. data bit transfer one data bit is transferred during each clock pulse. the serial interface clock pulse is provided by the master. the data must be stable during the high period of the serial clock?it can only change when the two-wire se rial interface clock is low. data is trans- ferred eight bits at a time, fo llowed by an acknowledge bit. acknowledge bit the master generates the acknowledge clock pu lse. the transmitter (which is the master when writing, or the slave when reading) re leases the data line, and the receiver indi- cates an acknowledge bit by pulling the data line low during the acknowledge clock pulse. no-acknowledge bit the no-acknowledge bit is generated when the data line is not pulled down by the receiver during the acknowledge clock pulse. a no-acknowledge bit is used to terminate a read sequence.
mt9v111_ds rev. n 5/15 en 23 ?semiconductor components industries, llc,2015. mt9v111 - 1/4-inch soc vga digital image sensor two-wire serial interface sample write and read sequences (with saddr = 1) two-wire serial interface sample write and read sequences (with s addr = 1) 16-bit write sequence a typical write sequence for writing 16 bits to a register is shown in figure 16. a start bit given by the master, followed by the write address, starts the sequence. the image sensor will then give an acknowledge bit and expects the register address to come first, followed by the 16-bit data. after each eight-bit the image sensor will give an acknowledge bit. all 16 bits must be written before the register will be updated. after 16 bits are transferred, the register address is automatically incremente d, so that the next 16 bits are written to the next register. the master stops wr iting by sending a start or stop bit. figure 16: timing diagram showing a write to reg0x09 with value 0x0284 16-bit read sequence a typical read sequence is shown in figure . first the master has to write the register address, as in a write sequence. then a start bit and the read address specifies that a read is about to happen from the register. the master then clocks out the register data eight bits at a time. the master sends an acknow ledge bit after each eight-bit transfer. the register address is auto-incremented after ever y 16 bits is transferred. the data transfer is stopped when the master sends a no-acknowledge bit. figure 17: timing diagram showing a re ad from reg0x09; returned value 0x0284 sclk s data start ack 0xb8 addr ack ack ack stop reg0x09 1000 0100 0000 0010 sclk s data start ack 0xb8 addr 0xb9 addr 0000 0010 reg 0x09 ack ack ack stop 1000 0100 nack
mt9v111_ds rev. n 5/15 en 24 ?semiconductor components industries, llc,2015. mt9v111 - 1/4-inch soc vga digital image sensor two-wire serial interface sample write and read sequences (with saddr = 1) eight-bit write sequence all registers in the camera are treated and accessed as 16-bit, even when some registers do not have all 16-bits used. however, cert ain hosts only support 8-bit serial communi- cation access. the camera provides a special accommodation for these hosts. to be able to write one byte at a time to th e register a special register address is added. the 8-bit write is done by first writing the upper 8 bits to the desired register and then writing the lower 8 bits to the special regist er address (reg0x7f). the register is not updated until all 16 bits have been written. it is not possible to just update half of a register. in figure 18, a typical sequence for 8-bit writing is shown. the second byte is written to the special register (reg0x7f). figure 18: timing diagram showing a bytewise write to reg0x09 with value 0x0284 eight-bit read sequence to read one byte at a time the same special register address is used for the lower byte. the upper 8 bits are read from the desired register. by following this with a read from the special register (reg0x7f) the lower 8 bits are accessed, as shown in figure 19 the master sets the no-acknowledge bits. figure 19: timing diagram showing a bytewis e read from reg0x09; returned value 0x0284 stop reg0x7f ack start 0xb8 addr ack s data sclk ack ack ack ack reg0x09 0xb8 addr 0000 0010 1000 0100 start start 0xb9 addr sdata sclk stop nack ack ack ack reg0x09 start 0xb8 addr 0000 0010 start 0xb9 addr sdata sclk nack ack ack ack reg0x7f start 0xb8 addr 1000 0100
mt9v111_ds rev. n 5/15 en 25 ?semiconductor components industries, llc,2015. mt9v111 - 1/4-inch soc vga digital image sensor two-wire serial interface sample write and read sequences (with saddr = 1) two-wire serial bus timing the two-wire serial interface operation re quires a certain minimum of master clock cycles between transitions. these are specified below in master clock cycles. figure 20: serial host interface start condition timing figure 21: serial host interface stop condition timing note: all timing are in units of master clock cycle. figure 22: serial host interface data timing for write note: s data is driven by an off-chip transmitter. figure 23: serial host interface data timing for read note: s data is pulled low by the sensor, or allowed to be pulled high by a pull-up resistor off-chip. sclk 5 s data 4 sc lk 5 s data 4 4 4 5
mt9v111_ds rev. n 5/15 en 26 ?semiconductor components industries, llc,2015. mt9v111 - 1/4-inch soc vga digital image sensor two-wire serial interface sample write and read sequences (with saddr = 1) figure 24: acknowledge signal timing after an 8-bit write to the sensor figure 25: acknowledge signal timing after an 8-bit read from the sensor note: after a read, the master receiver must pull down s data to acknowledge receipt of data bits. when read sequence is complete, the master must generate a no acknowledge by leaving s data to float high. on the following cycle, a start or stop bit may be used. sc lk s ensor pulls d own s data pin 6 s data 3 sc lk s ensor tri-states s data pin (turns off pull d own) 7 s data 6
mt9v111_ds rev. n 5/15 en 27 ?semiconductor components industries, llc,2015. mt9v111 - 1/4-inch soc vga digital image sensor appendix b C overview of programming appendix b C overview of programming default sensor configuration in its default configuration, the sensor ou tputs up to 15 fps at 12 mhz master clock frequency. auto exposure, automatic white balance, 60hz flicker avoidance, defect correction, and automatic noise suppression in low light conditions are enabled. the frame rate is controlled by ae and can be slowed down to 5 fps in low light. lens shading correction is disabled. gamma correction uses gamma = 0.6. image data are output in ycbcr itu_r.bt.656 vga format, with y, cb, and cr values ranging from 16 to 240. the use of the non-default register settings shown in table 10 are recommended to opti- mize sensor performance in the above configuration. note: non-default register settings required for an optimal 30 fps, 27 mhz operation are shown in table 11 note: to obtain register settings for other frame ra tes and clock speeds, please contact a on semicon- ductor fae. auto exposure target image brightness and accuracy of ae are set by ifp r46[7:0] and r46[15:8], respectively. for example, to overexpose imag es, set ifp r46[7:0] = 120. to change image brightness on lcd in rgb preview mode , use ifp r52[15:8]. ae logic can be programmed to keep the frame rate constant or vary it within certain range, by writing to ifp r55[9:5] one of the values tabulated in table 12. the speed of ae is set using ifp r47. the speed should be high in preview modes and lower for video output to avoid sudden changes in brightness between frames. auto exposure is disabled by setting ifp r6[14] = 0. when ae, awb, and flicker avoidance are all disabled (ifp r6[14] = 0, ifp r6[1] = 0, and ifp r8[11] = 0), exposure and analog gains can be adjusted manually (see core registers r9, r12, and r43 through r46). table 10: non-default register settings optimizing 15 fps at 12 mhz operation core: r5 = 46, r7[4] = 0, r33 = 58369, r47 = 63414 ifp: r51= 5137, r56 = 2168, r57= 290, r59 = 1068, r62 = 4095, r64 = 7696, r65 = 5143, r66 = 4627, r67 = 4370, r68 = 28944, r69 = 29811 table 11: non-default register settings optimizing 30 fps at 27 mhz operation core: r5 = 132, r6 = 10, r7[4] = 0, r33 = 58369 ifp: r51 = 5137, r57 = 290, r59 = 1068, r62 = 4095, r89 = 504, r90 = 605, r92 = 8222, r93 = 10021, r100 = 4477 table 12: relation between ifp r55[9:5] setting and frame rate range minimum frame rate maximum frame rate = 15 fps maximum frame rate = 30 fps 30 fps n/a 4 15 fps 8 8 7.5 fps 16 16 5 fps 24 24
mt9v111_ds rev. n 5/15 en 28 ?semiconductor components industries, llc,2015. mt9v111 - 1/4-inch soc vga digital image sensor appendix b C overview of programming automatic white balance awb can be disabled by setting ifp r6[1]=0. use ifp r37[2:0] and r37[6:3] to speed up awb response. please note that speeding awb up may result in color oscillation. if necessary, awb range can be restricted by changing the upper limit in ifp r36[14:8] and lower limit in ifp r36[6:0]. flicker avoidance use ifp r91 to choose automatic/manual, 50hz/60hz flicker avoidance and ifp r8[11] = 0 to disable this feature. flash for flash programming, see ifp r152 description. decimation, zoom, and pan for output decimation progra mming, see ifp r165 descriptio n. table 13 provides a few examples. note: for fixed 2x upsize zoom, set core r30[0] = 1. interpolation use ifp r5[2:0] to adjust image sharpness. by default, sharpness is automatically reduced in low-light conditions (see ifp r5[3]). for rgb565 16-bit capture, set ifp r6[12] = 0 and ifp r5[3] = 0 to avoid contouring. special effects to switch from color to gray scale output , set ifp r8[5] = 1. contact a on semiconductor fae for register settings producing other special effects (e.g. sepia output). image mirroring to mirror images horizontally, set core r32[14 ] = 1 and ifp r8[0] = 1. to flip images verti- cally, set core r32[15] = 1 and ifp r8[1] = 1. test pattern see ifp r72 and ifp reg58[5:3] description. table 13: decimation, zoom, and pan ifp registers cif output (correct aspect ratio) qvga output 2:1 zoom qvga output 1:1 zoom r165 26 160 0 r166 586 320 640 r167 352 320 320 r168 0 120 0 r169 480 240 480 r170 288 240 240
mt9v111_ds rev. n 5/15 en 29 ?semiconductor components industries, llc,2015. mt9v111 - 1/4-inch soc vga digital image sensor appendix b C overview of programming gamma correction see table 14 and table for register settings required to setup non-default gamma correc- tion. please note that these settings determ ine output signal range. use ycbcr settings with itu_r btu-compatible devices. use yuv settings for jpeg capture and rgb preview; switching to yuv mode requires setting ifp r52 = 0 and ifp r53 = 65281. table 14: ycbcr settings gamma 0.45 0.5 0.55 0.6 (default) 0.7 1.0 ifp r83 12836 10781 8984 7700 5389 2052 ifp r84 23876 21563 19508 17709 14627 8208 ifp r85 39039 37495 35952 34409 31581 24640 ifp r86 49326 48553 47780 47008 45207 41088 ifp r87 57552 57551 57549 57548 57545 57536 table 15: yuv settings gamma 0.45 0.5 0.55 0.6 0.7 1.0 ifp r83 14377 12321 10267 8726 6159 2308 ifp r84 26957 24643 22331 20276 16680 9234 ifp r85 44432 42631 40831 39031 35945 27720 ifp r86 56005 54976 54202 53173 51371 46481 ifp r87 65260 65259 65257 65255 65252 65241
mt9v111_ds rev. n 5/15 en 30 ?semiconductor components industries, llc,2015. mt9v111 - 1/4-inch soc vga digital image sensor appendix b C overview of programming figure 26: 44-ball icsp package outline drawing notes: 1. all dimensions in millimeters. 2. icsp package information is preliminary. seating plane 7.00 0.075 3.50 0.05 2.25 2.25 encapsulant: epoxy image sensor die lid material: borosilicate glass 0.40 thickness optical area optical center package center 1.17 0.10 0.22 (for reference only) 0.100 (for reference only) 0.95 (for reference only) 5.30 ctr 4.50 3.584 ctr 3.500 0.075 ball a1 corner 5.30 ctr 2.688 ctr 3.400 0.075 3.50 0.05 0.75 typ 0.75 typ 7.00 0.075 0.375 0.075 0.575 0.050 0.175 (for reference only) c l c l 4.50 substrate material: plastic laminate solder ball material: 62% sn, 36% pb, 2%ag or 96.5% sn, 3%ag, 0.5% cu solder mask defined ball pads: ? 0.27 maximum rotation of optical area relative to package edges: 1o maximum tilt of optical area relative to : 0.3o 0.10 a a ball a1 id ball a1 ball a7 44x ?0.35 dimensions apply to solder balls post reflow. the pre- reflow diameter is ?0.33 pixel (0,0) b b maximum tilt of optical area relative to top of cover glass: 0.3o
mt9v111_ds rev. n 5/15 en 31 ?semiconductor components industries, llc,2015. mt9v111 - 1/4-inch soc vga digital image sensor revision history revision history rev. n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4/16/15 ? updated ?ordering information? on page 2 rev. m. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3/27/15 ? converted to on semiconductor template rev. l . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5/3/11 ? updated trademarks ? applied updated template rev. k . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6/10 ? updated to non-confidential rev. j. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5/10 ? updated to aptina template ? transfered registers to a separate document rev. h, production . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6/06 ? updated table 6, ?ifp register list,? on page 12 rev. g, production . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1/05 ?modified t oh definition in table 7, ?ac elec trical characteristics,? on page 16 ? updated figure 10, propagation delays for pixclk and data out signals, on page 17 rev. f, production . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8/04 ? updated 44-ball icsp package outline drawing rev. e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7/04 ? replaced 28-pin plcc package information with the 44-ball icsp ? updated table 12 (frame time) ? updated electrical specifications rev. d, preliminary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3/04 ? modify for external web posting - streamlined register descriptions ?add appendix b rev. c, preliminary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2/04 ? added key performance parameter table, update register tables, update electrical specification table, added figures (image center offset, die placement, 28-pin plcc package outline drawing and spectral response) rev. b, preliminary, draft . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1/04 ? format edits on 1/15/04
on semiconductor and the on logo are registered trademarks of semiconductor components industries, llc (scillc) or its subsidia ries in the united states and/or other countries. scillc owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. a listing of scillcs pr oduct/patent coverage may be accessed at www.onsemi.com/site/pdf/ patent-marking.pdf. scillc reserves the right to make changes without further noti ce to any products herein. scillc makes no warranty, representat ion or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaim s any and all liability, including without limitation special, consequential or incidental damages. typical parameters which may be provided in scillc data shee ts and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including typicals must be validated for each customer a pplication by customers technical experts. scillc does not convey any license under its patent rights nor the rights of others. sc illc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in whic h the failure of the scillc prod uct could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such uninte nded or unauthorized applicatio n, buyer shall indemnify and hol d scillc and its officers, employ ees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly o r indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to a ll applicable copyright laws and is not for resale in any manner. mt9v111 - 1/4-inch soc vga digital image sensor revision history mt9v111_ds rev. n 5/15 en 32 ?semiconductor components industries, llc,2015 . a-pix is a trademark of semiconductor components industries, llc (s cillc) or its subsidiaries in the united states and/or other countries. rev. a, preliminary, draft . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12/03 ? initial release of document

▲Up To Search▲

Price & Availability of MT9V111D00STCK82AC1K-305

	To Download MT9V111D00STCK82AC1K-305 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .